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S5N8944B
G.Lite ADSL Transceiver for CO and CPE
Preliminary Information (Revision 2.1) June 2000
SAMSUNG ELECTRONICS CONFIDENTIAL PROPRIETARY
Copyright (c) 2000 Samsung Electronics, Inc. All Rights Reserved
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
Contents
1. 2. 3. 4. 5. 6. 7. 8. 9. Features............................................................................................................................5 General Description .........................................................................................................5 Logical Symbol Diagram..................................................................................................6 Pin Configuration .............................................................................................................7 Pin Description.................................................................................................................8 Functional Description...................................................................................................11 I/O Timing Description ...................................................................................................13 Electrical Characteristics...............................................................................................17 Package Description ......................................................................................................20
CONFIDENTIAL
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
List of Figures
Figure 1: General Block Diagram ...................................................................................... 5 Figure 2: Logical Symbol Diagram of the S5N8944B ......................................................... 6 Figure 3: Pin Configuration of the S5N8944B .................................................................... 7 Figure 4: Functional Block Diagram of the S5N8944B ..................................................... 12 Figure 5: AFE Data I/F Timing Diagram........................................................................... 13 Figure 6: AFE Control I/F Timing Diagram....................................................................... 13 Figure 7: Motorola Read Cycle Timing Diagram .............................................................. 14 Figure 8: Motorola Write Cycle Timing Diagram .............................................................. 14 Figure 9: Intel Read Cycle Timing Diagram ..................................................................... 15 Figure 10: Intel Write Cycle Timing Diagram ................................................................... 15 Figure 11: Non-ATM I/F (Byte Mode) Timing Diagram ..................................................... 16 Figure 12: Non-ATM I/F (Envelope Mode) Timing Diagram ............................................. 16 Figure 13: ATM I/F (UTOPIA-2 Transmit) Timing Diagram............................................... 17 Figure 14: ATM I/F (UTOPIA-2 Receive) Timing Diagram................................................ 17 Figure 15: 160-QFP Package Diagram............................................................................ 20
CONFIDENTIAL
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
List of Tables
Table 1: Pin Description of the S5N8944B......................................................................... 8 Table 2: Absolute Maximum Ratings ............................................................................... 18 Table 3: Recommended Operating Conditions ................................................................ 18 Table 4: Power Dissipation.............................................................................................. 18 Table 5: DC Characteristics ............................................................................................ 19
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
1. Features
* Full Compliance with ITU-T G.Lite and G.hs * FDM based DMT Line Coding * Data Rate: Up to 3.5 Mbps for Downstream and 600 kbps for Upstream. * Reach: 5.4 km (18 kft) on 24 AWG and 4 km (13.5kft) on 26 AWG * Rate Adaptive Modem (steps of 32kbps) * Reed-Solomon Forward Error Correction with Interleaver * Frequency and Time Domain Equalizer * Support Fast Retraining Function * Support Network Management Function * Support Power Management Function * Host Interface (Intel/Motorola) and ATM(UTOPIA-2)/non-ATM Interface * 0.25m, 2.5V CMOS Technology * Operating Temperature: -40 C to 85 C * Package Type: 160-QFP
2. General Description
The S5N8944B is a complete ATM-based rate adaptive G.Lite ADSL modem solution with associated F/W and an Analog Front-End (S5N8943). The S5N8944B provides all the digital functions such as ATM TC, FEC codec with interleaver/de-interleaver, adaptive QAM codec, FFT/IFFT, equalizers, digital filters and so on. There are four interfaces for external communications; UTOPIA-2 interface for direct connection to ATM systems, serial interface for non-ATM applications, 16-bit ADC/DAC interface, and host interface for general CPUs like Intel or Motorola. The same chipset can be used at both sides of the link, Central Office and Customer Premises Equipment. The S5N8944B uses 17.664MHz Xtal oscillator as a master clock for CO side and 17.664MHz VCXO for CPE.
S5N8944
ATM or Non-ATM Digital Interface
S5N8943
Analog FrontEnd Line Driver Hybrid Phone Line
DMT Processor
Host
DSP
ROM ROM
Figure 1: General Block Diagram
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
3. Logical Symbol Diagram
S5N8944B
RESET_N XTAL_IN XTAL_OUT EXT_CLK PLL_FLT TEST_MODE TEST_SCN_EN CO_RT TX_SHOW RX_SHOW NTR TX_ADDR[4:0] TX_DATA[7:0] TX_CLK TX_ENB TX_SOC TX_CLAV RX_ADDR[4:0] RX_DATA[7:0] RX_CLK RX_ENB RX_SOC RX_CLAV HS_SEL HS_ADDR[9:0] HS_DATA[15:0] HS_CS_N HS_RD_N HS_WR_N HS_READY HS_INT HS_WAKEUP LD_TX_PWDN LD_RX_PWDN AFE_RESET_N AFE_SDI AFE_SDO AFE_SCK AFE_SEN_N AFE_BUSY
DAC_REF DAC_DATA[15:0] ADC_REF ADC_DATA[15:0] TL_TMS TL_TCK TL_TDI TL_TDO TL_TINTP TL_BMODE[1:0]
Figure 2: Logical Symbol Diagram of the S5N8944B
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
4. Pin Configuration
TX_DATA_1 TX_DATA_0 NTR RX_ENB RX_CLK RX_SOC RX_CLAV GND12 VDD12 RX_ADDR_4 RX_ADDR_3 RX_ADDR_2 RX_ADDR_1 RX_ADDR_0 RX_DATA_7 RX_DATA_6 RX_DATA_5 RX_DATA_4 RX_DATA_3 RX_DATA_2 GND13 VDD13 RX_DATA_1 RX_DATA_0 GND14 XTAL_OUT XTAL_IN VDD14 AVDD15 AGND15 AGND16 PLL_FLT AVDD16 AGND17 RESET_N TL_BMODE_0 TL_BMODE_1 TEST_MODE CO_RT HS_SEL 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
HS_CS_N HS_RD_N HS_WR_N HS_READY VDD1 GND1 HS_INT HS_WAKEUP HS_DATA_15 HS_DATA_14 HS_DATA_13 HS_DATA_12 HS_DATA_11 HS_DATA_10 GND2 VDD2 HS_DATA_9 HS_DATA_8 HS_DATA_7 HS_DATA_6 HS_DATA_5 HS_DATA_4 HS_DATA_3 HS_DATA_2 GND3 VDD3 HS_DATA_1 HS_DATA_0 HS_ADDR_9 HS_ADDR_8 HS_ADDR_7 HS_ADDR_6 HS_ADDR_5 HS_ADDR_4 GND4 VDD4 HS_ADDR_3 HS_ADDR_2 HS_ADDR_1 HS_ADDR_0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
S5N8944B
G.Lite ADSL Transceiver for CO and CPE (160-QFP)
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
TX_DATA_2 TX_DATA_3 VDD11 GND11 TX_DATA_4 TX_DATA_5 TX_DATA_6 TX_DATA_7 TX_ADDR_0 TX_ADDR_1 TX_ADDR_2 TX_ADDR_3 TX_ADDR_4 TX_CLAV TX_SOC TX_CLK TX_ENB VDD10 GND10 TL_TINTP TL_TDO TL_TDI TL_TCK TL_TMS VDD9 GND9 RX_SHOW TX_SHOW LD_RX_PWDN LD_TX_PWDN AFE_BUSY AFE_RESET_N DAC_DATA_15 DAC_DATA_14 GND8 VDD8 DAC_DATA_13 DAC_DATA_12 DAC_DATA_11 DAC_DATA_10
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DAC_DATA_8 DAC_DATA_7 DAC_DATA_6 DAC_DATA_5 DAC_DATA_4 DAC_DATA_3 DAC_DATA_2 VDD7 GND7 DAC_DATA_1 DAC_DATA_0 DAC_REF EXT_CLK ADC_DATA_0 ADC_DATA_1 ADC_DATA_2 ADC_DATA_3 ADC_DATA_4 ADC_DATA_5 VDD6 GND6 ADC_DATA_6 ADC_DATA_7 ADC_DATA_8 ADC_DATA_9 ADC_DATA_10 ADC_DATA_11 ADC_DATA_12 ADC_DATA_13 ADC_DATA_14 ADC_DATA_15 VDD5 GND5 ADC_REF AFE_SCK AFE_SEN_N AFE_SDI AFE_SDO TEST_SCN_EN
Figure 3: Pin Configuration of the S5N8944B
CONFIDENTIAL
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
5. Pin Description
Table 1: Pin Description of the S5N8944B No 155 147 146 67 152 158 41 159 93 94 123 108 109 110 111 112 113 114 115 116 119 120 121 122 105 104 106 107 130 131 132 133 134 135 136 137 138 139 Name RESET_N XTAL_IN XTAL_OUT EXT_CLK PLL_FLT TEST_MODE TEST_SCN_EN CO_RT TX_SHOW RX_SHOW NTR TX_ADDR_4 TX_ADDR_3 TX_ADDR_2 TX_ADDR_1 TX_ADDR_0 TX_DATA_7 TX_DATA_6 TX_DATA_5 TX_DATA_4 TX_DATA_3 TX_DATA_2 TX_DATA_1 TX_DATA_0 TX_CLK TX_ENB TX_SOC TX_CLAV RX_ADDR_4 RX_ADDR_3 RX_ADDR_2 RX_ADDR_1 RX_ADDR_0 RX_DATA_7 RX_DATA_6 RX_DATA_5 RX_DATA_4 RX_DATA_3 I/O I I O I O I I I O O I/O Description System Master Reset (Active Low) System Master Clock (17.664MHz Xtal Oscillator for CO, VCXO for CPE) External Clock for Test (Not Used in Normal Mode, Pull-Down) PLL Pump Out [0] Normal Mode, [1] Test Mode Scan Enable (Set to `0' in Normal Mode) [0] CO, [1] CPE Tx Showtime (Active High. Connect to LED) Rx Showtime (Active High. Connect to LED) ATM Network Timing Reference (8KHz) (I: CO_RT=1, O: CO_RT=0)
I
Utopia Tx Address [4:0]
I
Utopia Tx Data [7:0]
I I I OZ
Utopia Tx Clock (25MHz) Utopia Tx Enable Utopia Tx Start of Cell Utopia Tx Cell Available
I
Utopia Rx Address [4:0]
OZ
Utopia Rx Data [7:0]
CONFIDENTIAL
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
140 143 144 125 124 126 127 160 29 30 31 32 33 34 37 38 39 40 9 10 11 12 13 14 17 18 19 20 21 22 23 24 27 28 1 2 3 4 7 8 91 92 RX_DATA_2 RX_DATA_1 RX_DATA_0 RX_CLK RX_ENB RX_SOC RX_CLAV HS_SEL HS_ADDR_9 HS_ADDR_8 HS_ADDR_7 HS_ADDR_6 HS_ADDR_5 HS_ADDR_4 HS_ADDR_3 HS_ADDR_2 HS_ADDR_1 HS_ADDR_0 HS_DATA_15 HS_DATA_14 HS_DATA_13 HS_DATA_12 HS_DATA_11 HS_DATA_10 HS_DATA_9 HS_DATA_8 HS_DATA_7 HS_DATA_6 HS_DATA_5 HS_DATA_4 HS_DATA_3 HS_DATA_2 HS_DATA_1 HS_DATA_0 HS_CS_N HS_RD_N HS_WR_N HS_READY HS_INT HS_WAKEUP LD_TX_PWDN LD_RX_PWDN
I I OZ OZ I
Utopia Rx Clock (25MHz) Utopia Rx Enable Utopia Rx Start of Cell Utopia Rx Cell Available Host Interface Type Selection [0] Motorola, [1] Intel
I
Host Address [9:0]
B
Host Data [15:0]
I I I OZ O OZ O O
Host Chip Select (Active Low) Motorola: Not Used Intel: Host Read Enable (Active Low) Motorola: [0] Write Enable, [1] Read Enable Intel: Write Enable (Active Low) Motorola: DTACK (Active Low) Intel: Ready (Active High) Motorola: IRQ (Active Low) Intel: INT (Active High) Host Wakeup [0] Active, [Hi-Z] Disable Tx Line Driver Power-down (Active High) Rx Line Driver Power-down (Active High)
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
89 43 42 45 44 90 68 88 87 84 83 82 81 80 79 78 77 76 75 74 73 70 69 46 49 50 51 52 53 54 55 56 57 58 61 62 63 64 65 66 97 98 99 100 101 AFE_RESET_N AFE_SDI AFE_SDO AFE_SCK AFE_SEN_N AFE_BUSY DAC_REF DAC_DATA_15 DAC_DATA_14 DAC_DATA_13 DAC_DATA_12 DAC_DATA_11 DAC_DATA_10 DAC_DATA_9 DAC_DATA_8 DAC_DATA_7 DAC_DATA_6 DAC_DATA_5 DAC_DATA_4 DAC_DATA_3 DAC_DATA_2 DAC_DATA_1 DAC_DATA_0 ADC_REF ADC_DATA_15 ADC_DATA_14 ADC_DATA_13 ADC_DATA_12 ADC_DATA_11 ADC_DATA_10 ADC_DATA_9 ADC_DATA_8 ADC_DATA_7 ADC_DATA_6 ADC_DATA_5 ADC_DATA_4 ADC_DATA_3 ADC_DATA_2 ADC_DATA_1 ADC_DATA_0 TL_TMS TL_TCK TL_TDI TL_TDO TL_TINTP O I O O O I O AFE Reset (Active Low) AFE Serial Input Data (Pull-Up) AFE Serial Output Data AFE Serial Clock AFE Serial Enable (Active Low) AFE Serial Busy (Active High, Pull-Down) DAC Data Reference (4.416MHz)
O
DAC Data [15:0]
I
Not Used in Normal Mode (Pull-Down)
I
ADC Data [15:0]
I I I OZ O
TeakLite JTAG Test Mode Selection TeakLite JTAG Test Clock TeakLite JTAG Test Data In TeakLite JTAG Test Data Out TeakLite TJAM Interrupt to Host
157
TL_BMODE_1 I
TeakLite Boot Mode Selection [0] Reset, [1] Boot from Host [2] Boot from JTAG, [3] Self-Booting
CONFIDENTIAL
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
156 5 26 48 60 85 103 118 142 149 153 16 36 72 96 129 148 6 15 25 35 47 59 71 86 95 102 117 128 141 145 150 151 154 TL_BMODE_0 VDD1 VDD3 VDD5 VDD6 VDD8 VDD10 VDD11 VDD13 AVDD15 AVDD16 VDD2 VDD4 VDD7 VDD9 VDD12 VDD14 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 AGND15 AGND16 AGND17
P1
2.5V Supply Voltage
P1
2.5V Analog Supply Voltage
P1
3.3V Supply Voltage
P0
Digital Ground
P0
Analog Ground
I O OZ B P1 P0
= Input = Output = Tri-state Output = Bi-direction = Power = Ground
6. Functional Description
The G.Lite ADSL modem consists of two main chips; ADSL Transceiver chip (S5N8944) and Analog Front-End chip (S5N8943). The Analog Front-End provides an analog interface with line
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
drivers and hybrid components to connect the PSTN. The ADSL Transceiver provides all the digital functions as depicted in Figure 4. The input bit stream is divided into bit slices and they are fed into the QAM which are allocated to 128 subchannels according to the bit loading table. The bit slices are then converted to frequency-domain complex samples by the QAM encoders. The 256 complex samples are changed to 256 time-domain samples by IFFT. The Tx filter performs band separation and interpolation functions. The received signals are attenuated and distorted in terms of both phase and amplitude. PLL fixes the phase errors within 4 samples using the 276kHz pilot tone transmitted from the CO side. The ones over 4 samples are fixed by the sync recovery algorithm using a known synchronization symbol. The TEQ is a filter that adaptively alters the channel so that the impulse response is reduced to the length of the cyclic prefix which will be removed prior to FFT. The FEQ is a one tap complex adaptive filter for each subchannel, which adjusts the gains and phases of the received signals. The equalizers are adaptively updated due to the transmission channel environment. In FDM-based DMT (Discrete MultiTone) modulation, the frequency band, 0 to 552kHz, is divided into 128 equi-spaced subchannels, of which 26kHz (#6) to 134kHz (#31) is allocated for the upstream, and 142kHz (#33) to 548kHz (#127) for the downstream. The Nyquist rate, therefore, should be 1.104MHz(276kHz) . DMT inherently transmits an optimized time-variable spectrum. This spectrum is adjusted according to the desired data rate and the transmission characteristics (transfer function and noise spectrum) on each and every subchannel. For this, CO and CPE transmit 128 4kHz-wide tone downstream and upstream respectively to each other during initialization. They measure the quality of each of these received tones and then decide whether a tone has sufficient quality to be used for further transmission and, if so, how much data this tone should carry relative to the other tones that are used. They inform the bit loading result to each other.
ATM or Non-ATM
ATM Framer
FEC Codec
QAM Codec
IFFT 256/64
TX Filter
DAC
Host
DSP
FEQ
FFT 256/64
TEQ
RX Filter
ADC
Figure 4: Functional Block Diagram of the S5N8944B
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
7. I/O Timing Description
t3 DAC_REF (4.416MHz) DAC_DAT[15:0] (4.416MHz) ADC_DAT[15:0] (2.208MHz) t4
t1
t2 Min 30 1 15 15 Max Unit ns ns ns ns
Parameter t1 t2 t3 t4
Description ADC_DAT setup to DAC_REF ADC_DAT hold after DAC_REF DAC_DAT setup to DAC_REF DAC_DAT hold after DAC_REF Figure 5: AFE Data I/F Timing Diagram
t2 AFE_SEN_N AFE_SCL (1.104MHz) AFE_SDO AFE_SDI AFE_BUSY
t3
CS1
CS0
A4
A0
RW
D15 D15
D14 D14
t1
D0 D0
Parameter t1 t2 t3
Description AFE_SDI setup to AFE_SCL AFE_SEN_N before AFE_SCL AFE_SEN_N from AFE_SCL Figure 6: AFE Control I/F Timing Diagram
Min 30 30 15
Max
Unit ns ns ns
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
HS_ADDR[9:0] HS_DATA[15:0] HS_CS_N HS_WR_N HS_READY (DTACKN) t2 t3
VALID
t1
t5 t4
Parameter t1 t2 t3 t4 t5
Description HS_ADDR setup to HS_CS_N HS_WR_N before HS_CS_N HS_DATA valid from HS_READY HS_READY hi-Z from HS_CS_N HS_DATA hold after HS_CS_N
Min 0 0 1
Max
10 5 5
Unit ns ns ns ns ns
Figure 7: Motorola Read Cycle Timing Diagram
HS_ADDR[9:0] HS_DATA[15:0] HS_CS_N t2 HS_WR_N t4 HS_READY (DTACKN) t1 t3
VALID
t5
Parameter t1 t2 t3 t4 t5
Description HS_ADDR setup to HS_CS_N HS_WR_N before HS_CS_N HS_DATA valid from HS_CS_N HS_READY hi-Z from HS_CS_N HS_DATA hold after HS_CS_N
Min 0 0 1 5
Max
50 5
Unit ns ns ns ns ns
Figure 8: Motorola Write Cycle Timing Diagram
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
HS_ADDR[9:0] HS_DATA[15:0] HS_CS_N HS_RD_N t5 HS_READY t1
VALID
t2 t3
t6
t4
Parameter t1 t2 t3 t4 t5 t6
Description HS_ADDR setup to HS_CS_N HS_CS_N before HS_RD_N HS_DATA valid from HS_RD_N HS_CS_N from HS_RD_N HS_READY from HS_RD_N HS_DATA hold after HS_RD_N Figure 9: Intel Read Cycle Timing Diagram
Min 0 0 0 0
Max
170 20 5
Unit ns ns ns ns ns ns
HS_ADDR[9:0] HS_DATA[15:0] HS_CS_N HS_WR_N t5 HS_READY t4
VALID
t1
t2
t3
t6
Parameter t1 t2 t3 t4 t5 t6
Description HS_ADDR setup to HS_CS_N HS_CS_N before HS_WR_N HS_DATA valid from HS_WR_N HS_CS_N from HS_WR_N HS_READY from HS_WR_N HS_DATA hold after HS_WR_N Figure 10: Intel Write Cycle Timing Diagram
Min 0 0 0 0 5
Max
50 20
Unit ns ns ns ns ns ns
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
t1 RX_DATA_3 (TX_SCL) RX_DATA_4 (TX_SDAV) RX_ADDR_0 (TX_SDA) RX_DATA_1 (RX_SCL) RX_DATA_2 (RX_SDAV) RX_DATA_0 (RX_SDA)
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
Parameter t1
Description TX_SCL frequency
Min 1
Max 25
Unit MHz
Figure 11: Non-ATM I/F (Byte Mode) Timing Diagram
t1 RX_DATA_3 (TX_SCL) RX_DATA_4 (TX_SDAV) RX_ADDR_0 (TX_SDA) RX_DATA_1 (RX_SCL) RX_DATA_2 (RX_SDAV) RX_DATA_0 (RX_SDA)
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
Parameter t1
Description RX_SCL frequency
Min 1
Max 25
Unit MHz
Figure 12: Non-ATM I/F (Envelope Mode) Timing Diagram
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
t1 TX_CLK (25MHz) TX_ADDR[4:0] TX_CLAV TX_ENB TX_DATA[7:0] TX_SOC
(ATM0) (ATM1) P46 P47 P48 H1 H2 H3
00
1F
01
1F
02
1F
03
1F
Parameter t1
Description Signal Hold after TX_CLK
Min 5
Max 10
Unit ns
Figure 13: ATM I/F (UTOPIA-2 Transmit) Timing Diagram t1 RX_CLK (25MHz) RX_ADDR[4:0] RX_CLAV RX_ENB RX_DATA[7:0] RX_SOC
(ATM0) (ATM1) P45 P46 P47 P48 H1 H2
00
1F
01
1F
02
1F
03
1F
Parameter t1
Description Signal Hold after RX_CLK
Min 5
Max 10
Unit ns
Figure 14: ATM I/F (UTOPIA-2 Receive) Timing Diagram
8. Electrical Characteristics
CONFIDENTIAL
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
Table 2: Absolute Maximum Ratings Symbol VDD VIN VOUT ILATCH TSTG Parameter DC Supply Voltage DC Input Voltage DC Output Voltage Latch-up Current Storage Temperature Rating 3.6 2.5V Input Buffer 3.3V Input Buffer 5V-tolerant Input Buffer 2.5V Buffer 3.3V Buffer 200 -65 to 150 Unit 3.6 4.6 6.5 3.6 4.6
V
mA C
Table 3: Recommended Operating Conditions Symbol VDD Parameter DC Supply Voltage Analog Core DC Supply Voltage Operating Temperature (Ambient) 2.5V I/O 3.3V I/O 5V-tolerant I/O 2.5V Core Industrial Rating 2.3 to 2.7 3.0 to 3.6 3.0 to 3.6 2.55% -40 to 85 Unit V C
TA
Table 4: Power Dissipation Symbol PD Parameter Power Dissipation Min Typ 0.35 Max 0.4 Unit W
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
Table 5: DC Characteristics Symbol VIH VIL VOH VOL VT VT+ VTVH IIH IIL IOZ IOS IDD CIN COUT Parameters Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Switching Threshold Schmitt Trigger, Positive-going Threshold Schmitt Trigger, Negative-going Threshold Schmitt Trigger , VT+ - VTInput High Current (VIN=VDD) Input Low Current (VIN=VSS) Tri-state Output Leakage Current Output Short Circuit Current Quiescent Supply Current Input Capacitance Output Capacitance Min 1.7(0.7VDD) 1.9(2.4) 0.6(0.8) 0.5 -10 10* -10 -50(-60)* -10 -55 Typ 0.5VDD 0.65(0.575) 25(33)* -25(-33)* Max 0.7(0.3VDD) 0.5(0.4) 1.9(2.0) 0.8(0.65) 10 50(60)* 10 -10* 10 55 100 4 4 Unit
V
A
pF
NOTES: 1. () - in case of 5V-tolerant 2. * - input buffer with pull-up or pull-down. 3. CIN and COUT exclude package parastics.
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
9. Package Description
A B
A
B
A: 31.200.25 B: 28.000.10
#160
#1 0.65BSC
(1.325) 0.300.08
M 0.12
3.400.25 0~7
4.07MAX 0.10
0.73~1.03
0.25MIN
Figure 15: 160-QFP Package Diagram
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Preliminary Information (Rev.2.1 )
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
Revision History
Revision No. 1.0 Date 2000-02-01 2000-06-15 Description KS8944A (Rev.1) Released. S5N8944B (Rev.2) Released. - Internal Memories Reduced. - Input Pin, NOISE_DET (41) changed to TEST_SCN_EN. - Output Pin, GP_OUT_1 (93) changed to TX_SHOW. - Output Pin, GP_OUT_0 (94) changed to RX_SHOW. - TC byte alignment problem fixed. - TX_DATA latched at the rising edge of TX_CLK. 160-QFP Package Description Added. Pin Description Modified.
2.0
2.1
2000-06-22
IMPORTANT NOTICE
The information furnished by Samsung Electronics in this document is belived to be accurate and reliable. However, no resposibility is assumed by Samsung Electronics for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Samsung Electronics. Samsung Electronics reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete.
For More Information Tel: (82)-(31)-209-8301, Fax: (82)-(31)-209-8309 E-mail: kimil@sec.samsung.com http://www.intl.samsungsemi.com
Copyright (c) 2000 Samsung Electronics, Inc. All Rights Reserved
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Preliminary Information (Rev.2.1 )

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